A micro-chip-module is an assembly of receptacles for receiving predefined integrated circuit chips. The receptacles are located on a high density signal carrier (HDSC) or other type of micro-chip-module substrate. When the integrated circuit chips are loaded into the receptacles, the input/output pins of each chip are interconnected with the input/output pins of other ones of the chips, as well as with input/output connectors for the micro-chip-module, by a series of metal interconnects located on the high density signal carrier. The metal interconnects connect the pins of the loaded chips in such a way as to make the micro-chip-module suitable as a discrete component in a particular electronic system, typically a computer or other data processing system. For example, Digital Equipment Corporation's 3MAX++micro-chip-module is used as the central processing unit (CPU) in a number of computer systems.
However, during fabrication of the micro-chip-module, errors in the construction of the interconnects may occur. In order to ensure that a particular micro-chip-module will perform properly, it must be verified that each interconnect does not have an open or short circuit.
In the past, there have been several attempts at developing a method for doing so. These include the boundary scan method and the resistance measurement method, both of which are well known to those skilled in the art.
The boundary scan method involves generating a patterned input signal at an input port of the micro-chip-module. The signal is then passed in series through each interconnect so that the input signal traverses all the interconnects on the micro-chip-module. The patterned input signal is passed from interconnect to interconnect by circuitry which is added to each integrated circuit chip specifically for this purpose. The patterned signal is finally observed at an output port of the micro-chip-module to determine if there are any open or short circuits in the series of interconnects.
As suggested above, one problem with this method is that it requires the integrated circuit chips to be manufactured with additional circuitry. In some cases, this additional circuitry takes up approximately 10% of the entire chip area. Another problem associated with this method is that it cannot be determined which interconnect is faulty. Since the signal is passed in series through each interconnect and only detected at the output port, if the output signal pattern differs from what would be output by a properly functioning micro-chip-module, it cannot be determined which interconnect has an open or short circuit.
The resistance measurement method on the other hand involves the use of an apparatus with multiple probes to measure simultaneously the resistance of multiple interconnects. From the observed resistance measurements, it can be determined which interconnects have an open or short circuit. However, there is a significant problem with this method. Complex micro-chip-modules require a large number of interconnects. As a result, a large number of probes must be used in the apparatus described above. However, it is often impractical to make test apparatus with the required number of probes, and sequential probing of subsets of the interconnections using a smaller number of probes is also not practical because it is slow and because it may also fail to find short circuits.
Since each micro-chip-module may be worth hundreds or thousands of dollars, it would be very beneficial to have a test methodology that not only provides a pass/fail indication for each micro-chip-module, but also provides a specific indication of each failed node and the nature of the failure. For instance, if the test methodology were able to identify the interconnection failure specifically, such as with a message that "interconnect node X has an open circuit," that would greatly facilitate the process of deciding which micro-chip-modules can be repaired as well as the process of repairing the micro-chip-modules with repairable faults.
Therefore, there is a need for a method and system for ensuring interconnect integrity in a micro-chip-module which (1) does not unnecessarily add area to the integrated circuit chips of the micro-chip-module, (2) pinpoints which interconnects are faulty, (3) is practical to implement, and (4) tests for all possible open and short circuits.